The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Jan. 23, 2017
Applicants:

Imsolution Co., Ltd., Hsinchu County, TW;

Yukihiro Nagai, Sapporo, Hokkaido, JP;

Riichiro Shirota, Fujisawa, Kanagawa, JP;

Hiroshi Watanabe, Yokohama, Kanagawa, JP;

Inventors:

Te-Chang Tseng, Zhubei, TW;

Yukihiro Nagai, Sapporo, JP;

Riichiro Shirota, Fujisawa, JP;

Hiroshi Watanabe, Yokohama, JP;

Assignee:

IM Solution Co., Ltd., Zhubei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/16 (2006.01); H01L 27/11582 (2017.01); H01L 29/49 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 29/16 (2013.01); H01L 29/42344 (2013.01); H01L 29/42348 (2013.01); H01L 29/513 (2013.01); G11C 5/063 (2013.01); G11C 16/0433 (2013.01); G11C 16/0466 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01);
Abstract

A cheap and high performance 1.5 transistor-type flash memory highly compatible externally of a memory region has a sacrifice film formed on a substrate. A U-shaped groove is formed on the sacrifice film, where multiple insulating films are laminated. The multiple insulating films includes a silicon nitride film as a charge storage layer. Low resistive material is disposed on the multiple insulating films to form a control gate. The select gate is formed on the insulating film on a side of the control gate in a self-aligned manner. Semiconductor regions opposite in conductivity to the substrate on both sides of the adjoining control gate and the select gate form a source and a drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with the adjoining control gate and the select gate between the source and the drain. In a MOS-type transistor with the control gate, the threshold voltage is changeable according to injection/emission of the charge to the silicon nitride as the charge storage layer, and thus work as a non-volatile memory.


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