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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9899364 B1

PDFFull Text
Date of Patent:
Feb. 20, 2018

Filed:

Jul. 23, 2015

Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

James Walter Blatchford, Richardson, TX (US);

Thomas J. Aton, Dallas, TX (US);

Assignee:

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);

Attorneys:

Jacqueline J. Garner

Charles A. Brill

Frank D. Cimino

Primary Examiner:

Marcos D Pizarro

Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823425 (2013.01); H01L 21/823437 (2013.01); H01L 27/088 (2013.01); H01L 29/78 (2013.01); H01L 2924/10157 (2013.01);
Abstract

An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.

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Quick Actions:

Blatchford, James. (2018). Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two (U.S. Patent No. 9899364). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9899364

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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