The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Mar. 09, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Michael Mostovoy, San Ramon, CA (US);

Gokul Kumar, San Jose, CA (US);

Ning Ye, San Jose, CA (US);

Hem Takiar, Fremont, CA (US);

Venkatesh P. Ramachandra, San Jose, CA (US);

Vinayak Ghatawade, Bangalore, IN;

Chih-Chin Liao, Changhua, TW;

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/49 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 24/43 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/49174 (2013.01); H01L 2224/49175 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.


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