The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Jun. 06, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Gun-ho Chang, Seoul, KR;

Tae-je Cho, Yongin-si, KR;

Jong-bo Shim, Asan-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/27002 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92224 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06582 (2013.01);
Abstract

A semiconductor package includes a package member and a stress controlling layer. The package member includes an encapsulation layer and at least one chip. The encapsulation layer encapsulates the at least one chip. The stress controlling layer is disposed on a surface of the package member. The stress controlling layer has an internal stress to the extent that the stress controlling layer prevents the package member from having warpage.


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