The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Dec. 07, 2012
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Qiuxia Xu, Beijing, CN;

Huilong Zhu, Poughkeepsie, NY (US);

Gaobo Xu, Beijing, CN;

Huajie Zhou, Beijing, CN;

Qingqing Liang, Lagrangeville, NY (US);

Dapeng Chen, Beijing, CN;

Chao Zhao, Kessel-lo, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823828 (2013.01); H01L 21/28088 (2013.01); H01L 21/28185 (2013.01); H01L 21/28194 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/7833 (2013.01); H01L 29/665 (2013.01);
Abstract

There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.


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