The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2018
Filed:
Sep. 14, 2015
United Microelectronics Corp., Hsin-Chu, TW;
Chun-Hsien Wu, New Taipei, TW;
Chen-Hsien Hsu, Hsinchu County, TW;
Wei-Jen Wang, Tainan, TW;
Chien-Fu Chen, Miaoli County, TW;
Chien-Hung Chen, Taipei, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.