The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Jul. 02, 2015
Applicant:

Nan Ya Pcb Corporation, Taoyuan, TW;

Inventors:

Wei-Ta Fu, Taoyuan, TW;

Kuo-Chang Wu, Yilan County, TW;

Yu-Chih Lin, Taoyuan, TW;

Assignee:

Nan Ya PCB Corp., Taoyuan County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4602 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H05K 1/188 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92244 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01); H05K 3/427 (2013.01); H05K 2201/10181 (2013.01); H05K 2201/10636 (2013.01); H05K 2203/072 (2013.01); H05K 2203/1469 (2013.01); Y02P 70/611 (2015.11);
Abstract

An embedded component substrate and methods for fabricating the same are provided. The embedded component substrate includes a substrate having at least one cavity, a first surface, and a second surface. The embedded component substrate also includes at least one electronic component formed in the at least one cavity. The embedded component substrate also includes a first wiring layer formed in the space between a sidewall of the at least one electronic component and a sidewall of the at least one cavity. The first wiring layer extends from the first surface of the substrate to the sidewall of the at least one cavity, and directly contacts the at least one electronic component.


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