The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Sep. 04, 2014
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Yoshitaka Yamamoto, Yamatokoriyama, JP;

Tetsuhiro Tanaka, Atsugi, JP;

Takayuki Inoue, Sagamihara, JP;

Hideomi Suzawa, Atsugi, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 27/12 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 11/24 (2006.01); G11C 7/04 (2006.01); G11C 14/00 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); G11C 11/24 (2013.01); G11C 16/0466 (2013.01); G11C 16/3404 (2013.01); H01L 27/1225 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/7881 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); G11C 7/04 (2013.01); G11C 14/0054 (2013.01);
Abstract

A method for adjusting threshold of a semiconductor device is provided. In a plurality of semiconductor devices each including a semiconductor, a source or drain electrode electrically in contact with the semiconductor, a gate electrode, and a charge trap layer between a gate electrode and the semiconductor, a state where the potential of the gate electrode is set higher than the potential of the source or drain electrode while the semiconductor devices are heated at 150° C. or higher and 300° C. or lower is kept for one second or longer to trap electrons in the charge trap layer, so that the threshold is increased and Icut is reduced. Here, the potential difference between the gate electrode and the source or drain electrode is set so that it is different between the semiconductor devices, and the thresholds of the semiconductor devices are adjusted to be appropriate to each purpose.


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