The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Aug. 08, 2016
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Senaka Kanakamedala, Milpitas, CA (US);

Rahul Sharangpani, Fremont, CA (US);

Raghuveer S. Makala, Campbell, CA (US);

Somesh Peri, San Jose, CA (US);

Yao-Sheng Lee, Tampa, FL (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/115 (2017.01); H01L 21/768 (2006.01); H01L 29/788 (2006.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 27/11529 (2017.01); H01L 27/11556 (2017.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/5283 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01);
Abstract

After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.


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