The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Aug. 25, 2015
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Takeshi Sonehara, Yokkaichi, JP;

Masaru Kito, Kuwana, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/11582 (2017.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H01L 27/1157 (2013.01); H01L 27/11575 (2013.01);
Abstract

According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end connected to the substrate, has as its longer direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. Assuming at least one control gate electrode positioned in a lowermost layer of the plurality of control gate electrodes to be a first control gate electrode, the first control gate electrode comprises: a first portion; a second portion adjacent to the first portion; and a third portion connected to the first portion and the second portion.


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