The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

May. 14, 2015
Applicants:

Yeong-kwon Ko, Suwon-si, KR;

Tae-hyeong Kim, Suwon-si, KR;

Ji-hwang Kim, Cheonan-si, KR;

Sun-kyoung Seo, Suwon-si, KR;

Tae-je Cho, Yongin-si, KR;

Inventors:

Yeong-Kwon Ko, Suwon-si, KR;

Tae-Hyeong Kim, Suwon-si, KR;

Ji-Hwang Kim, Cheonan-si, KR;

Sun-Kyoung Seo, Suwon-si, KR;

Tae-Je Cho, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 25/065 (2006.01); B23K 26/00 (2014.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); B23K 26/0057 (2013.01); H01L 25/0657 (2013.01); H01L 21/76898 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/5448 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06593 (2013.01);
Abstract

Semiconductor devices and methods for manufacturing a semiconductor device include a first semiconductor substrate in which a first scribe line region and a first chip region are defined, a first alignment mark inside the first semiconductor substrate and in the first scribe line region so as to be spaced apart from an upper side of the first semiconductor substrate, a second semiconductor substrate on the first semiconductor substrate and in which a second scribe line region and a second chip region are defined, and a second alignment mark inside the second semiconductor substrate and in the second scribe line region so as to be spaced apart from an upper side of the second semiconductor substrate, wherein the second semiconductor substrate is on the first semiconductor substrate so that positions of the first alignment mark and the second alignment mark correspond to each other.


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