The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2018
Filed:
Dec. 08, 2016
Applicant:
Nxp B.v., Eindhoven, NL;
Inventors:
Chung Hsiung Ho, Kaohsiung, TW;
Wen-Hsuan Lin, Kaohsiung, TW;
Assignee:
NXP B.V., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/28 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3192 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/293 (2013.01); H01L 23/544 (2013.01); H01L 23/562 (2013.01); H01L 24/08 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/0401 (2013.01);
Abstract
A semiconductor device includes a device die having a top surface, a bottom surface, and sidewalls between the top and bottom surfaces. A first protective layer covers at least the top surface and the sidewalls of the die. A thickness of the first protective layer on the sidewalls near the top surface is greater than a thickness of the first protective layer on the sidewalls die near the bottom surface.
Ho, Chung. (2018). Wafer-level chip scale package with side protection (U.S. Patent No. 9892989). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9892989
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile