The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Jan. 19, 2016
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Neeraj Parik, San Jose, CA (US);

Gurjeet S. Saund, Saratoga, CA (US);

Rakesh L. Notani, Sunnyvale, CA (US);

Robert E. Jeter, Santa Clara, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 7/22 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0629 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 13/1689 (2013.01); G11C 7/222 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.


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