The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2018
Filed:
Jul. 03, 2016
Applicant:
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Inventor:
Hideki Makiyama, Tokyo, JP;
Assignee:
Renesas Electric Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/115 (2017.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/08 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 21/28282 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/0649 (2013.01); H01L 29/0852 (2013.01); H01L 29/66833 (2013.01); H01L 29/7838 (2013.01);
Abstract
Performances of a semiconductor device are improved. The semiconductor device has: a gate electrode formed on an SOI layer of an SOI substrate via a gate insulating film having a charge storage film therein; an n-type semiconductor region and a p-type semiconductor region respectively formed on SOI layers on both sides of the gate electrode. A memory cell MC serving as a non-volatile memory cell is formed of the gate insulating film, the gate electrode, the n-type semiconductor region and the p-type semiconductor region.