The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Dec. 23, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Roger Gramunt, Portland, OR (US);

Rammohan Padmanabhan, Beaverton, OR (US);

Ramon Matas, Portland, OR (US);

Neal S. Moyer, Hillsboro, OR (US);

Benjamin C. Chaffin, Portland, OR (US);

Avinash Sodani, Portland, OR (US);

Alexey P. Suprun, Beaverton, OR (US);

Vikram S. Sundaram, Beaverton, OR (US);

Chung-Lun Chan, Hillsboro, OR (US);

Gerardo A. Fernandez, Beaverton, OR (US);

Julio Gago, Barcelona, ES;

Michael S. Yang, Hillsboro, OR (US);

Aditya Kesiraju, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/44 (2006.01); G06F 12/12 (2016.01); G06F 12/122 (2016.01); G06F 9/48 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 12/122 (2013.01); G06F 9/384 (2013.01); G06F 9/3851 (2013.01); G06F 9/3855 (2013.01); G06F 9/3859 (2013.01); G06F 9/4806 (2013.01); G06F 2212/62 (2013.01);
Abstract

In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.


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