The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Mar. 15, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Maxim Loktyukhin, Folsom, CA (US);

Robert Valentine, Kiryat Tivon, IL;

Julian C. Horn, Acton, MA (US);

Mark J. Charney, Lexington, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 7/38 (2006.01); G06F 9/00 (2006.01); G06F 9/44 (2006.01); G06F 9/30 (2006.01); G06F 9/45 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30196 (2013.01); G06F 8/52 (2013.01); G06F 9/3017 (2013.01); G06F 9/30029 (2013.01); G06F 9/30058 (2013.01); G06F 9/30145 (2013.01); G06F 9/4552 (2013.01);
Abstract

Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the novel test instruction through a just-in-time compiler. Some embodiments also fuse the novel test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.


Find Patent Forward Citations

Loading…