The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Jan. 12, 2016
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Kandabara N. Tapily, Albany, NY (US);

Genji Nakamura, Kai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66772 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/78618 (2013.01); H01L 29/78654 (2013.01); H01L 29/78696 (2013.01);
Abstract

Embodiments of the invention describe a method for forming a nanowire structure on a substrate. According to one embodiment, the method includes a) depositing a first semiconductor layer on the substrate, b) etching the first semiconductor layer to form a patterned first semiconductor layer, c) forming a dielectric layer across the patterned first semiconductor layer, and d) depositing a second semiconductor layer on the patterned first semiconductor layer and on the dielectric layer. The method further includes e) repeating a)-d) at least once, f) following e), repeating a)-c) once, g) etching the patterned first semiconductor layers, the dielectric layers, and the second semiconductor layers to form a fin structure, and h) removing the patterned first semiconductor layers from the fin structure.


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