The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Mar. 03, 2016
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;

Inventors:

Toshiaki Sakata, Matsumoto, JP;

Yasushi Niimura, Matsumoto, JP;

Shunji Takenoiri, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 21/266 (2013.01);
Abstract

A first parallel pn layer having a first n-type region and a first p-type region junctioned alternately and repeatedly is disposed in an element active portion. The first parallel pn layer has a striped planar layout. A second parallel pn layer having a second n-type region and a second p-type region junctioned alternately and repeatedly is disposed in a high voltage structure. The second parallel pn layer has a striped planar layout in a direction identical to that of the first parallel pn layer. An intermediate region having a third parallel pn layer and a fourth parallel pn layer of a lower impurity quantity than the first parallel pn layer is disposed between the first and second parallel pn layers, and formed by diffusing impurity implanting regions becoming the first and the second parallel pn layers formed separated from each other to a region in which no impurity is ion-implanted.


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