The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

May. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andreas Duevel, Almstedt, DE;

Telesphor Kamgaing, Chandler, AZ (US);

Valluri R. Rao, Saratoga, CA (US);

Uwe Zillmann, Braunschweig, DE;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01F 5/00 (2006.01); H01F 27/06 (2006.01); G09G 5/00 (2006.01); H01L 49/02 (2006.01); H01F 7/08 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01F 17/00 (2006.01); H01L 21/768 (2006.01); H01L 27/06 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 28/10 (2013.01); H01F 17/0006 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5227 (2013.01); H01L 27/0688 (2013.01); H01F 2017/002 (2013.01); H01L 27/08 (2013.01); H01L 2224/4813 (2013.01);
Abstract

A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.


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