The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Oct. 29, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Michael Bauer, Nittendorf, DE;

Ludwig Heitzer, Falkensfels, DE;

Christian Stuempfl, Schmidgaden, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 25/16 (2006.01); H01L 23/485 (2006.01); H01L 21/02 (2006.01); H01L 21/78 (2006.01); H01L 25/00 (2006.01); H01L 25/04 (2014.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 21/022 (2013.01); H01L 21/02164 (2013.01); H01L 21/02266 (2013.01); H01L 21/78 (2013.01); H01L 23/485 (2013.01); H01L 24/94 (2013.01); H01L 25/04 (2013.01); H01L 25/50 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/273 (2013.01); H01L 2224/274 (2013.01); H01L 2224/291 (2013.01); H01L 2224/3201 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/83801 (2013.01); H01L 2224/94 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/206 (2013.01); H01L 2924/2064 (2013.01);
Abstract

A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first semiconductor die and a first solder interconnect layer applied to a main face of the first semiconductor die. The second semiconductor chip has a second semiconductor die, an insulating layer applied to a main face of the second semiconductor die, and a second solder interconnect layer applied to the insulating layer. The method further includes attaching the first semiconductor chip with the first solder interconnect layer to a first carrier and attaching the second semiconductor chip with the second solder interconnect layer to a second carrier.


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