The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Jan. 23, 2017
Applicant:

Novatek Microelectronics Corp., Hsinchu, TW;

Inventors:

Jung-Fu Hsu, Hsinchu, TW;

Tai-Hung Lin, Hsinchu, TW;

Chang-Tien Tsai, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 27/02 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 24/48 (2013.01); H01L 23/50 (2013.01); H01L 24/05 (2013.01); H01L 24/49 (2013.01); H01L 27/0292 (2013.01); H01L 27/0296 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05088 (2013.01); H01L 2224/05095 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/4813 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48132 (2013.01); H01L 2224/48464 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/49113 (2013.01); H01L 2924/30205 (2013.01);
Abstract

An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.


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