The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Aug. 13, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chewn-Pu Jou, Hsinchu, TW;

Chien-Jung Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 29/78 (2006.01); H01L 27/07 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0617 (2013.01); H01L 27/0722 (2013.01); H01L 29/78 (2013.01); H01L 29/7838 (2013.01);
Abstract

An integrated circuit comprises a first doped region and a second doped region in a substrate. The second doped region is separated from the first doped region by a first spacing. The integrated circuit further comprises a dielectric layer over the substrate and a gate over the dielectric layer. The gate is positioned having the first doped region on a first substrate side of the gate and the second doped region on a second substrate side of the gate opposite the first substrate side of the gate. The integrated circuit also comprises a third doped region in the substrate separated from the first doped region by a second spacing. The integrated circuit further comprises a fourth doped region in the substrate. The gate and the third doped region are coupled with a first voltage supply, and the fourth doped region is coupled with a second voltage supply.


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