The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 2018
Filed:
Jul. 05, 2016
Dohyun Lee, Hwaseong-si, KR;
Youngwoo Park, Seoul, KR;
Junghoon Park, Yongin-si, KR;
Jaeduk Lee, Seongnam-si, KR;
Dohyun Lee, Hwaseong-si, KR;
Youngwoo Park, Seoul, KR;
Junghoon Park, Yongin-si, KR;
Jaeduk Lee, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.