The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Jun. 26, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Edward T. Grochowski, San Jose, CA (US);

Galina Ryvchin, Haifa, IL;

Michael Behar, Zichron Yaakov, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 15/8076 (2013.01); G06F 9/3001 (2013.01); G06F 9/30101 (2013.01); G06F 9/30145 (2013.01); G06F 15/8007 (2013.01);
Abstract

Instructions and logic provide SIMD vector packed histogram functionality. Some processor embodiments include first and second registers storing, in each of a plurality of data fields of a register lane portion, corresponding elements of a first and of a second data type, respectively. A decode stage decodes an instruction for SIMD vector packed histograms. One or more execution units, compare each element of the first data type, in the first register lane portion, with a range specified by the instruction. For any elements of the first register portion in said range, corresponding elements of the second data type, from the second register portion, are added into one of a plurality data fields of a destination register lane portion, selected according to the value of its corresponding element of the first data type, to generate packed weighted histograms for each destination register lane portion.


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