The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2018
Filed:
Oct. 19, 2015
Avary Holding (Shenzhen) Co., Limited, Shenzhen, CN;
Hongqisheng Precision Electronics (Qinhuangdao) Co., Ltd., Qinhuangdao, CN;
Garuda Technology Co., Ltd., New Taipei, TW;
Tzu-Chien Yeh, New Taipei, TW;
Avary Holding (Shenzhen) Co., Limited, Shenzhen, CN;
HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Qinhuangdao, CN;
GARUDA TECHNOLOGY CO., LTD., New Taipei, TW;
Abstract
A circuit board includes a core layer, at least one passive component, a first and a second conductive wire layers, at least one contact pad, and a resin packing layer. The core layer defines at least one through hole to receive the passive component. The first and the second conductive wire layers are connected to two opposite surfaces of the core layer. Each contact pad is positioned between and connected to one passive component and the first conductive wire layer. The resin packing layer is filled among the core layer, each passive component, each contact pad, the first and the second conductive wire layers. The resin packing layer can connect the first and the second conductive wire layers to the core layer, and connect the core layer, each passive component, and each contact pads to each other.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile