The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2018
Filed:
Nov. 06, 2015
Semiconductor Manufacturing International (Shanghai) Corporation;
Yi Liu, Shanghai, CN;
Jun Wang, Shanghai, CN;
Ying Ma, Shanghai, CN;
Bin Lu, Shanghai, CN;
Huijuan Cheng, Shanghai, CN;
Abstract
A semiconductor device includes a P-type substrate, and an N-well in the P-type substrate. A first N+ diffusion region is located in the P-type substrate, and a first P+ diffusion region is located in the N-well. A second P+ diffusion region is located across a boundary between the P-type substrate and the N-well. A first gate electrode overlies the N-well between the first P+ diffusion regions and the second P+ diffusion region. A second gate electrode overlies the P-type substrate between the second P+ diffusion region and the first N+ diffusion region. The first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device. The first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS transistor. The second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode.