The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Nov. 14, 2014
Applicant:

Cavium, Inc., San Jose, CA (US);

Inventors:

Shubhendu Sekhar Mukherjee, Southborough, MA (US);

David Asher, Sutton, MA (US);

Bradley Dobbie, Cambridge, MA (US);

Thomas Hummel, Holliston, MA (US);

Daniel Dever, North Brookfield, MA (US);

Assignee:

CAVIUM, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 12/10 (2016.01); G06F 12/1027 (2016.01); G06F 12/1009 (2016.01); G06F 12/0815 (2016.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 12/0815 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 13/404 (2013.01); G06F 13/4234 (2013.01); G06F 2212/50 (2013.01); G06F 2212/60 (2013.01); G06F 2212/65 (2013.01); G06F 2212/68 (2013.01); G06F 2212/683 (2013.01);
Abstract

Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.


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