The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Mar. 31, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Tsvika Kurts, Haifa, IL;

Eilon Hazan, Hogla, IL;

Sean T. Baartmans, Portland, OR (US);

Marcus R. Winston, Aloha, OR (US);

Rony Ghattas, Hillsboro, OR (US);

Arie Bernstein, Kfar Saba, IL;

Todd M. Witter, Orangevale, CA (US);

Marcelo Yuffe, Binyamina, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/34 (2006.01); G06F 11/30 (2006.01); G06F 11/32 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3476 (2013.01); G06F 11/3024 (2013.01); G06F 11/323 (2013.01); G06F 11/3409 (2013.01); G06F 11/3636 (2013.01); G06F 11/3656 (2013.01); G06F 11/3466 (2013.01);
Abstract

A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.


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