The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Sep. 04, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Anand S. Ramalingam, Beaverton, OR (US);

Dale J. Juenemann, North Plains, OR (US);

Pranav Kalavade, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G06F 3/06 (2006.01); G06F 12/0804 (2016.01); G06F 12/0868 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0647 (2013.01); G06F 3/061 (2013.01); G06F 3/0685 (2013.01); G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G11C 11/5628 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/214 (2013.01); G06F 2212/225 (2013.01); G06F 2212/261 (2013.01); G06F 2212/7203 (2013.01); G11C 2211/5648 (2013.01);
Abstract

Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.


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