The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Aug. 12, 2016
Applicant:

Tokyo Seimitsu Co., Ltd., Tokyo, JP;

Inventors:

Takashi Ishimoto, Tokyo, JP;

Yuji Shigesawa, Tokyo, JP;

Akira Yamaguchi, Tokyo, JP;

Takashi Motoyama, Tokyo, JP;

Takenori Takahashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 21/683 (2006.01); G01R 31/00 (2006.01); H01L 21/67 (2006.01); H01L 21/687 (2006.01); G01R 1/067 (2006.01); H01L 21/677 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2875 (2013.01); G01R 1/06705 (2013.01); G01R 31/00 (2013.01); H01L 21/677 (2013.01); H01L 21/67103 (2013.01); H01L 21/67109 (2013.01); H01L 21/67115 (2013.01); H01L 21/683 (2013.01); H01L 21/68742 (2013.01);
Abstract

The present invention provides a semiconductor wafer inspection apparatus and a semiconductor wafer inspection method that can suppress warpage in a semiconductor wafer due to a temperature difference between the mounting surface of a table and the semiconductor wafer. In a prober of the present invention, a semiconductor wafer is heated to have a second temperature which is equal to or lower than a first temperature in a preheating step using an oven, and then the semiconductor wafer is placed on a mounting surface of a table which is heated to the first temperature. Thus, because a temperature difference between the mounting surface of the table and the semiconductor wafer is reduced in the prober, it is possible to suppress warpage in the semiconductor wafer that occurs right after the semiconductor wafer is placed on the mounting surface.


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