The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Dec. 21, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jeffrey P. Gambino, Westford, VT (US);

Richard S. Graf, Gray, ME (US);

Sudeep Mandal, Bangalore, IN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 21/02 (2006.01); H01C 7/10 (2006.01); H01C 7/112 (2006.01); H01C 17/00 (2006.01); H01C 7/12 (2006.01); H01L 27/02 (2006.01); H01L 23/64 (2006.01); H01L 21/762 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/62 (2006.01); H01L 29/06 (2006.01); H01C 17/12 (2006.01);
U.S. Cl.
CPC ...
H01L 28/24 (2013.01); H01C 7/1013 (2013.01); H01C 7/112 (2013.01); H01C 7/12 (2013.01); H01C 17/006 (2013.01); H01C 17/12 (2013.01); H01L 21/022 (2013.01); H01L 21/02175 (2013.01); H01L 21/02266 (2013.01); H01L 21/762 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/62 (2013.01); H01L 23/647 (2013.01); H01L 27/0248 (2013.01); H01L 29/0649 (2013.01);
Abstract

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.


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