The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
Dec. 04, 2015
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Anthony K. Stamper, Burlington, VT (US);
Vibhor Jain, Essex Junction, VT (US);
Renata A. Camillo-Castillo, Williston, VT (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/267 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 29/20 (2006.01); H01L 29/161 (2006.01); H01L 27/092 (2006.01); H01L 29/737 (2006.01);
U.S. Cl.
CPC ...
H01L 29/267 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 27/092 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/737 (2013.01); H01L 2224/18 (2013.01);
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.