The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
Dec. 14, 2014
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/336 (2006.01); H01L 29/10 (2006.01); H01L 27/12 (2006.01); H01L 23/522 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1083 (2013.01); H01L 23/5223 (2013.01); H01L 27/124 (2013.01); H01L 27/1214 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01); H01L 29/0649 (2013.01); H01L 29/402 (2013.01); H01L 29/42372 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A method for manufacturing an isolation structure integrated with semiconductor device includes following steps. A substrate is provided. A plurality of trenched gates is formed in the substrate. A first insulating layer and a second insulating layer are sequentially deposited on the substrate. A first etching process is performed to remove portions of the second insulating layer to expose portions of the first insulating layer. A second etching process is then performed to remove the exposed second insulating layer to expose the trenched gates and to define at least an active region.