The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

Feb. 16, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ching-Wen Hung, Tainan, TW;

Wei-Cyuan Lo, Taichung, TW;

Ming-Jui Chen, Tainan, TW;

Chia-Lin Lu, Taoyuan, TW;

Jia-Rong Wu, Kaohsiung, TW;

Yi-Hui Lee, Taipei, TW;

Ying-Cheng Liu, Tainan, TW;

Yi-Kuan Wu, Kaohsiung, TW;

Chih-Sen Huang, Tainan, TW;

Yi-Wei Chen, Taichung, TW;

Tan-Ya Yin, Nantou County, TW;

Chia-Wei Huang, Kaohsiung, TW;

Shu-Ru Wang, Taichung, TW;

Yung-Feng Cheng, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/768 (2006.01); H01L 27/11 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823871 (2013.01); H01L 21/76802 (2013.01); H01L 21/76805 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 21/823821 (2013.01); H01L 23/535 (2013.01); H01L 27/0922 (2013.01); H01L 27/1104 (2013.01); H01L 27/1108 (2013.01); H01L 29/7851 (2013.01); H01L 29/7853 (2013.01);
Abstract

A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.


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