Memory system with mlc memory cells and partial page compression or reduction

Abstract

A memory system includes a memory device, the memory device including a memory cell array and a compression encoder, the memory cell array including a first plurality of multi level cells (MLCs). The memory device is configured to generate a first partial page by performing one or more first sensing operations on the first plurality of MLCs using one or more first reference voltages, output the first partial page, generate a second partial page by performing a second sensing operation on the first plurality of MLCs based on a second reference voltage, the second reference voltage having a different voltage level than the one or more first reference voltages, generate a compressed second partial page by compressing the second partial page using the compression encoder, and output the compressed second partial page.