The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
May. 09, 2016
Cadence Design Systems, Inc., San Jose, CA (US);
Meir Ovadia, Rosh Ha-ayin, IL;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method for generating a minimized combined scenario for use in simulation, from a post-silicon validation test that includes a combined scenario, may include obtaining a failed scenario loop of a scenario of the combined scenario that includes combined action scenarios that were executed in loops during a post-silicon validation test of a system on chip; and adding any loops of other scenarios of the combined scenario that were executed at least partially concurrently with the failed scenario loop, while discarding any loops of other scenarios of the combined scenario that were completed during the post-silicon validation test before the failed scenario loop or did not commence before the failed scenario loop was completed.