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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9858181 B1

PDFFull Text
Date of Patent:
Jan. 02, 2018

Filed:

Jun. 20, 2013

Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein

Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Yutaka Uematsu, Tokyo, JP;

Satoshi Muraoka, Tokyo, JP;

Hiroshi Kakita, Tokyo, JP;

Akio Idei, Tokyo, JP;

Yusuke Fukumura, Tokyo, JP;

Satoru Watanabe, Tokyo, JP;

Takayuki Ono, Tokyo, JP;

Taishi Sumikura, Tokyo, JP;

Yuichi Fukuda, Tokyo, JP;

Takashi Miyagawa, Tokyo, JP;

Michinori Naito, Tokyo, JP;

Hideki Osaka, Tokyo, JP;

Masabumi Shibata, Tokyo, JP;

Hitoshi Ueno, Tokyo, JP;

Kazunori Nakajima, Tokyo, JP;

Yoshihiro Kondo, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:

Mattingly & Malur, PC

Primary Examiner:

Charles Rones

Assistant Examiner:

Han Doan

Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 12/02 (2006.01); G11C 5/04 (2006.01); G11C 11/00 (2006.01); G06F 12/06 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 12/0638 (2013.01); G11C 5/04 (2013.01); G11C 7/1072 (2013.01); G11C 11/005 (2013.01); G11C 16/0491 (2013.01); G06F 2212/2532 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

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