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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9857981 B1

PDFFull Text
Date of Patent:
Jan. 02, 2018

Filed:

May. 20, 2016

Host interface controller and control method for storage device

Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

Lin Li, Beijing, CN;

Yunxing Dong, Beijing, CN;

Zhiqiang Hui, Beijing, CN;

Assignee:

VIA ALLIANCE SEMICONDUCTOR CO., LTD., Shanghai, CN;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Edward Dudek, Jr

Int. Cl.
CPC ...
G11C 7/10 (2006.01); G06F 12/08 (2016.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 9/44 (2006.01); G06F 12/0862 (2016.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0605 (2013.01); G06F 3/061 (2013.01); G06F 3/0611 (2013.01); G06F 3/0632 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0685 (2013.01); G06F 9/4406 (2013.01); G06F 12/0292 (2013.01); G06F 12/0862 (2013.01); G11C 11/4082 (2013.01); G11C 11/4091 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/602 (2013.01); G06F 2212/6022 (2013.01);
Abstract

A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

Find Patent Forward Citations

Li, Lin. (2018). Host interface controller and control method for storage device (U.S. Patent No. 9857981). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9857981

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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