The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Nov. 27, 2012
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Huilong Zhu, Poughkeepsie, NY (US);

Zhijiong Luo, Poughkeepsie, NY (US);

Haizhou Yin, Poughkeepsie, NY (US);

Qingqing Liang, Lagrangeville, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/311 (2013.01); H01L 21/32115 (2013.01); H01L 21/845 (2013.01); H01L 29/0692 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/1608 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/3083 (2013.01);
Abstract

The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (), a BOX layer () and an SOI layer (); forming a basic fin structure from an SOI layer; forming source/drain regions () on both sides of the basic fin structure; forming a fin structure between the source/drain regions () from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.


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