The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Feb. 02, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Shiang-Yu Chen, Hsinchu, TW;

Kuo-Ming Wu, Hsinchu, TW;

Yi-Chun Lin, Hsinchu, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/26 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7835 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 29/26 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/7836 (2013.01);
Abstract

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.


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