The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Jul. 02, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Long-Shih Lin, Zhubei, TW;

Kun-Ming Huang, Taipei, TW;

Ming-Yi Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 21/8222 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66325 (2013.01); H01L 21/8222 (2013.01); H01L 29/0634 (2013.01); H01L 29/0696 (2013.01); H01L 29/0808 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/66659 (2013.01); H01L 29/66931 (2013.01); H01L 29/7394 (2013.01); H01L 29/42368 (2013.01); H01L 29/66681 (2013.01); H01L 29/7393 (2013.01); H01L 29/7816 (2013.01); H01L 29/7824 (2013.01); H01L 29/7835 (2013.01);
Abstract

A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.


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