The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Jan. 14, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Ji-Hoon Choi, Seongnam-si, KR;

Dong-Kyum Kim, Suwon-si, KR;

Jin-Gyun Kim, Suwon-si, KR;

Su-Jin Shin, Hwaseong-si, KR;

Sang-Hoon Lee, Seongnam-si, KR;

Ki-Hyun Hwang, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/792 (2006.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/28008 (2013.01); H01L 21/28282 (2013.01); H01L 27/1157 (2013.01); H01L 29/7926 (2013.01); H01L 21/02252 (2013.01); H01L 21/02255 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.


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