The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2017
Filed:
Oct. 28, 2015
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Chih-Chung Wang, Hsinchu, TW;
Shih-Yin Hsiao, Chiayi County, TW;
Wen-Fang Lee, Hsinchu, TW;
Nien-Chung Li, Hsinchu, TW;
Shu-Wen Lin, Hsinchu County, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H01L 21/321 (2006.01); H01L 29/49 (2006.01); H01L 29/06 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); H01L 21/28035 (2013.01); H01L 21/31051 (2013.01); H01L 21/32115 (2013.01); H01L 21/32139 (2013.01); H01L 27/088 (2013.01); H01L 29/0653 (2013.01); H01L 29/4916 (2013.01); H01L 29/66545 (2013.01);
Abstract
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.