The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2017
Filed:
Jul. 21, 2016
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Meng-Han Lin, Hsinchu, TW;
Chih-Ren Hsieh, Changhua, TW;
Chen-Chin Liu, Hsinchu, TW;
Zhen Yang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate. The isolation region surrounds an active region of the substrate in plan view and includes an insulating material. A first dielectric layer is formed over the active region. A mask layer is formed on at least a part of a border line between the isolation region and the active region. The mask layer covers a part, but not entirety, of the first dielectric layer and a part of the isolation region surrounding the active region. The first dielectric layer not covered by the mask layer is removed such that a part of the active region is exposed. After the first dielectric layer is removed, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. A gate electrode is formed over the gate dielectric layer.