The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Nov. 22, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventor:

Po-Chao Tsao, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823431 (2013.01); H01L 27/0611 (2013.01); H01L 27/0629 (2013.01); H01L 28/20 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/408 (2013.01); H01L 29/7816 (2013.01); H01L 29/7817 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode covering on the substrate. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure.


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