The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Oct. 21, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dong-Hyuk Kim, Seongnam-si, KR;

Geo-Myung Shin, Seoul, KR;

Dong-Suk Shin, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/165 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02532 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/02639 (2013.01); H01L 21/823431 (2013.01); H01L 21/823456 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.


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