The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Aug. 08, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Emad Al-Momani, Austin, TX (US);

Jack Mumbo, Beaverton, OR (US);

Srikanth Mothukuri, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H05K 2201/1056 (2013.01); H05K 2201/10318 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10393 (2013.01); H05K 2201/10409 (2013.01); H05K 2201/10598 (2013.01); H05K 2201/10719 (2013.01); H05K 2201/10734 (2013.01);
Abstract

Apparatuses, systems and methods associated with electrical fast transient tolerant input/output (I/O) communication (e.g., universal serial bus (USB)) design are disclosed herein. In embodiments, an apparatus to mount an integrated circuit (IC) package, may include a printed circuit board (PCB), a plurality of pogo pins, and a mounting mechanism. The plurality of pogo pins may be mounted to electrical contacts of the PCB, the plurality of pogo pins may be coupled to the electrical contacts at first ends of the plurality of pogo pins and may be to couple to the IC package at second ends of the plurality of pogo pins. The mounting mechanism may position the IC package on the second ends of the plurality of pogo pins. Other embodiments may be described and/or claimed.


Find Patent Forward Citations

Al-Momani, Emad. (2017). Pogo pin integrated circuit package mount (U.S. Patent No. 9844144). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9844144

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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