The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Dec. 30, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Wei Cheng Wu, Zhubei, TW;

I-Ching Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 27/115 (2017.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 21/28282 (2013.01); H01L 21/32115 (2013.01); H01L 21/32133 (2013.01); H01L 27/11573 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01);
Abstract

An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. The logic gate is arranged within a high κ dielectric layer. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate. The control transistor further comprises a charge trapping layer underlying the control gate. The control and select gates are a first material, and the logic gate is a second material. A high-κ-last method for manufacturing the IC is also provided.


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