The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2017
Filed:
Dec. 14, 2012
Nvidia Corporation, Santa Clara, CA (US);
Ge Yang, Dublin, CA (US);
Hwong-Kwo Lin, Palo Alto, CA (US);
Xi Zhang, San Jose, CA (US);
Jiani Yu, Fremont, CA (US);
Haiyan Gong, San Jose, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.