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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9842183 B1

PDFFull Text
Date of Patent:
Dec. 12, 2017

Filed:

Sep. 29, 2015

Methods and systems for enabling concurrent editing of electronic circuit layouts

Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Arnold Ginetti, Antibes, FR;

Gerard Tarroux, Villeneuve-Loubet, FR;

Jean-Noel Pic, Valbonne, FR;

Olivier Arnaud, Peymeinade, FR;

Devendra Deshpande, Noida, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:

Eric L. Sophir

Dentons US LLP

Primary Examiner:

Helen Rossoshek

Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 17/24 (2006.01); G06F 3/0481 (2013.01); G06F 17/30 (2006.01); G06F 3/0484 (2013.01); G06F 7/00 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5022 (2013.01); G06F 3/0481 (2013.01); G06F 3/04842 (2013.01); G06F 7/00 (2013.01); G06F 17/24 (2013.01); G06F 17/30312 (2013.01); G06F 17/30979 (2013.01);
Abstract

Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.

Find Patent Forward Citations

Ginetti, Arnold. (2017). Methods and systems for enabling concurrent editing of electronic circuit layouts (U.S. Patent No. 9842183). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9842183

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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